Custom Timing and Verification CAD Engineer

Summary

Apple's custom silicon is among the most sophisticated in the world — and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom Timing CAD team builds and owns the flows, tools, and methodologies that make that verification possible. We are looking for an entry-level engineer who is eager to learn, technically curious, and excited to work at the intersection of circuit design and CAD engineering.

Description

In this role, you will support and develop flows for two of the most critical sign-off disciplines in custom IC design — transistor-level timing verification using NanoTime and formal verification using ESP. You will partner closely with analog and digital designers across multiple programs and technology nodes, helping them set up flows, debug issues, and achieve clean sign-off. The work you do will directly shape the quality and schedule of Apple's most advanced chips.

Responsibilities

Develop, maintain, and improve CAD flows and automation scripts for NanoTime and ESP
Support design teams in setting up timing and verification runs, interpreting results, and resolving tool and methodology issues
Drive timing and formal verification closure in collaboration with circuit designers
Contribute to methodology documentation and guidelines adopted across programs and design organizations
Engage with EDA vendors to report issues, evaluate new features, and drive tool improvements
Build automation to improve flow efficiency, reduce runtime, and scale support across concurrent programs

Minimum Qualifications

BS degree (MS preferred) in Electrical Engineering, Computer Engineering, Computer Science, or related field
Programming or scripting experience in Perl, Python, TCL, or similar language
Foundational understanding of digital or custom IC design at transistor level and static timing analysis through coursework or internship experience

Preferred Qualifications

Exposure to tools such as NanoTime, ESP, PrimeTime, or HSPICE is a plus
Knowledge of dynamic logic, memory arrays, or mixed-signal circuit techniques
Familiarity with SPICE netlists, device models, and parasitic extraction formats such as DSPF or SPF
Knowledge of formal verification tools and concepts and experience with SystemVerilog RTL
Interest in AI/ML-driven innovation for CAD workflows
Strong communicator who can accurately describe technical issues and follow them through to resolution
Highly motivated and able to work independently in a fast-paced environment

Pay & Benefits — Sunnyvale, California, United States

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,300 and $194,700, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Application Deadline

Apple accepts applications to this posting on an ongoing basis.