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Senior CAD Manager — RTL-to-GDS Methodology & Infrastructure, Annapurna Labs

Posted Aug 4, 2026

Role at a glance

Salary
$239.6K – $324.1K/yr
Location
Cupertino, California, United States
Work arrangement
Hybrid
Employment
Full-time
Experience
15+ years of experience in semiconductor CAD/EDA, methodology, or physical design
Education
Bachelor's, Master's, PhD

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Role Summary

AI-generated

The Senior CAD Manager will lead and scale a multi-site CAD/EDA organization responsible for RTL-to-GDS methodology, flow development, analytics, and the digital backend toolchain. The role supports next-generation SoC tape-outs at advanced nodes by improving time-to-tape-out, PPA and signoff quality, and visibility into project health.

What You'll Do

  • Define and drive the multi-year roadmap for RTL-to-GDS flows, including methodology bring-up for new technology nodes, foundry PDKs, and...
  • Own EDA tool strategy and vendor relationships, including evaluations, benchmarking, license forecasting, peak-load planning, and cost...
  • Build and scale CAD flow frameworks, regression infrastructure, run management, release engineering, CI/CD-style practices, and version...
  • Own CAD dashboards and analytics for PPA tracking, run health, signoff QoR trending, tape-out readiness scorecards, and compute/license...
  • Build, mentor, and scale a multi-site CAD organization while establishing operating cadence, technical reviews, knowledge-sharing...
  • Partner with physical design, DV, RTL, package, IP, IT, and executive stakeholders on flow capabilities, technology readiness, schedule...

Generated from the employer's posting. Verify important details before applying.

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Qualifications

Required

  • Bachelor's degree in electrical engineering, computer engineering, or equivalent
  • 15+ years of experience in semiconductor CAD/EDA, methodology, or physical design
  • 5+ years of experience in people management or technical leadership of engineering teams
  • Experience taking SoCs through tape-out at advanced nodes (7 nm or below) using industry-standard digital implementation flows
  • Experience with RTL-to-GDS toolchains including synthesis, place-and-route, static timing analysis, parasitic extraction, power/IR analysis, and physical verification
  • Experience with low-power design flows (UPF/CPF), MMMC corners, and POCV/SSTA at advanced nodes
  • Experience with scripting and automation (Tcl, Python, or Perl) and version control systems (Git or Perforce)
  • Experience scaling CAD compute infrastructure (LSF, Slurm, or equivalent) and managing license capacity at scale

Preferred

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field
  • Experience with AI/ML-driven flow automation or ML features in EDA tools (e.g., predictive QoR/runtime models)
  • Experience with package- and system-aware flows (2.5D/3D IC, chiplets, UCIe) and SI/PI co-design
  • Experience with cloud-based EDA workflows and hybrid on-prem/cloud compute strategy
  • Experience with formal verification, RTL signoff, and emulation flows
  • Track record of presenting at industry forums (DAC, SNUG, CDNLive, ISPD) or contributing to EDA standards bodies
  • Demonstrated ability to build and lead geographically distributed engineering teams across multiple time zones

Original job description

Content provided by the employer

Annapurna Labs is hiring a Senior CAD Manager to build, lead, and scale the CAD/EDA organization driving RTL-to-GDS methodology, flow development, and analytics across multiple sites. This is a strategic leadership role responsible for defining the multi-year roadmap for digital implementation, signoff, and physical verification; building and scaling a geographically distributed CAD team; and partnering with design, DV, IT, and EDA vendors to enable next-generation SoC tape-outs at advanced nodes (5 nm / 3 nm / 2 nm and below).

You will own the technical direction and operational health of the full digital backend toolchain — synthesis, place-and-route, STA, power/IR, EM, and physical verification — along with the license, dashboard, and automation infrastructure that supports it. Success in this role means a CAD organization that materially accelerates time-to-tape-out, raises PPA and signoff quality, and gives engineering leadership data-driven visibility into project health.

Key job responsibilities
Define and drive the multi-year roadmap for RTL-to-GDS flows across synthesis, place-and-route, STA, signoff, and physical verification; lead methodology bring-up for new technology nodes, foundry PDKs, and IP integration.
Own the EDA tool strategy and vendor relationships; lead structured evaluations, benchmarking, license forecasting, peak-load planning, and cost optimization in partnership with procurement and finance.
Build and scale the CAD environment — flow frameworks, regression infrastructure, run management, release engineering, CI/CD-style practices, and version control supporting multiple technology nodes.
Own the strategy for CAD dashboards and analytics: PPA tracking, run health, signoff QoR trending, tape-out readiness scorecards, and compute/license efficiency metrics.
Build, mentor, and scale a multi-site CAD organization; establish operating cadence, technical reviews, knowledge-sharing practices, engineering standards, and quality bars for CAD deliverables.
Partner with physical design, DV, RTL, package, IP, and IT teams to align flow capabilities to program commitments; engage executive stakeholders on technology readiness, schedule risk, and capacity planning.

Basic Qualifications

- Bachelor's degree in electrical engineering, computer engineering, or equivalent
- 15+ years of experience in semiconductor CAD/EDA, methodology, or physical design
- 5+ years of experience in people management or technical leadership of engineering teams
- Experience taking SoCs through tape-out at advanced nodes (7 nm or below) using industry-standard digital implementation flows
- Experience with RTL-to-GDS toolchains including synthesis, place-and-route, static timing analysis, parasitic extraction, power/IR analysis, and physical verification
- Experience with low-power design flows (UPF/CPF), MMMC corners, and POCV/SSTA at advanced nodes
- Experience with scripting and automation (Tcl, Python, or Perl) and version control systems (Git or Perforce)
- Experience scaling CAD compute infrastructure (LSF, Slurm, or equivalent) and managing license capacity at scale

Preferred Qualifications

- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field
- Experience with AI/ML-driven flow automation or ML features in EDA tools (e.g., predictive QoR/runtime models)
- Experience with package- and system-aware flows (2.5D/3D IC, chiplets, UCIe) and SI/PI co-design
- Experience with cloud-based EDA workflows and hybrid on-prem/cloud compute strategy
- Experience with formal verification, RTL signoff, and emulation flows
- Track record of presenting at industry forums (DAC, SNUG, CDNLive, ISPD) or contributing to EDA standards bodies
- Demonstrated ability to build and lead geographically distributed engineering teams across multiple time zones

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.



USA, CA, Cupertino - 239,600.00 - 324,100.00 USD annually
amazon

About the company

amazon

Large Enterprise

Amazon is a global leader in e-commerce and cloud computing, founded in 1994 by Jeff Bezos. Initially starting as an online bookstore, it has since expanded its offerings to include a vast range of products and services, including electronics, fashion, and digital content. With Amazon Web Services (AWS), the company also provides powerful cloud solutions to businesses around the world. Known for its innovation, customer-centric approach, and commitment to operational efficiency, Amazon continues to shape the future of retail and technology, consistently seeking new ways to enhance customer experiences.