Intel

Intel

Posted via Workday

Memory Electrical Validation Engineer

Posted Sep 3, 2026

Role at a glance

Job function
Engineering & R&D Electrical, Electronics & Controls Engineering
Salary
$190.6K – $269.1K/yr
Location
Hillsboro, Oregon, United States
Work arrangement
Hybrid
Employment
Internship
Education
Bachelors or Master's degree in electrical engineering or physics or computer engineering or another relevant field

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Role Summary

AI-generated

This role defines and executes electrical validation for memory I/O interfaces and mixed-signal architectures supporting Intel silicon products. The work focuses on electrical performance, signal integrity, system-level margin, production goals, and resolving electrical issues and test escapes.

What You'll Do

  • Define electrical validation strategy for memory IO interfaces.
  • Validate circuit analog performance, electrical signal integrity compliance, and system-level margin.
  • Analyze, validate, debug, and optimize MRC steps and values.
  • Develop validation procedures, analysis, designs, infrastructure, and systems margin validation.
  • Analyze customer returns to improve yields and drive test escape closure.
  • Perform debug to identify root causes and resolve functional and triage failures for electrical issues.

Generated from the employer's posting. Verify important details before applying.

View full posting

Qualifications

Minimum qualifications include a bachelor's or master's degree in electrical engineering, physics, computer engineering, or another relevant field; 5+ years of Memory/DDR technology experience; 5+ years of system-level and memory-interface validation and debug experience; and 5+ years with JEDEC memory protocols and test methodologies.

Required

  • Bachelor's or Master's degree in electrical engineering, physics, computer engineering, or another relevant field
  • 5+ years of experience in Memory/DDR technology
  • 5+ years of hands-on validation and debug experience at system level and memory interfaces
  • 5+ years of experience with industry-standard JEDEC memory protocols and test methodologies

Preferred

  • Understanding platform level signal integrity and power integrity technologies
  • Experience with validation of high-speed I/O interfaces, including understanding of Tx, Rx, PLL, DLL, Clocking, and Equalization
  • Knowledge of computer architecture and software/firmware architecture
  • Hands-on experience of validation & debug using Oscilloscopes, Signal generators, BERT, and Logic analyzers
  • Familiarity of Server/Xeon Memory RAS features
  • Python scripting/programming skills
  • In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation concepts
  • Familiarity with Memory Reference Code (MRC), DDR training algorithms

Original job description

Content provided by the employer

Job Details:

Job Description: 

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

Note:

This role requires regular onsite presence to fulfill essential job responsibilities.

  • Defines electrical validation strategy for memory IO interfaces to achieve optimized electrical performance and meet product production goals.
  • Validates circuit analog performance, electrical signal integrity compliance to industry standard specifications, and system level margin for stable operation and production target prediction.
  • Defines MRC (Memory Reference Code) requirements for validation and margin optimization and analyzes, validates, debugs, and optimizes MRC steps and values to optimize margins and quality.
  • Conducts and participates in multidisciplinary research in the design, development, testing, validation, and utilization of memory IO and mixed signal architectures inclusive of industry standard datacom applications and custom Intel interfaces.
  • Develops procedures, analysis, and designs for validation, validation infrastructure, and systems margin validation.
  • Analyzes internal and external customer returns with emphasis on improving yields and driving test escape closure.
  • Applies and uses independent evaluation to select components and equipment based on analysis of specifications, performance, and reliability.
  • Performs debug to identify root causes and resolves all functional and triage failures for electrical issues.
  • Tests interactions between various electrical design features using validation infrastructure.
  • Applies understanding of DFT and DFM to collaborate with architecture, design, and presilicon verification teams to ensure capability to validate and test IO architecture implementations.
  • Prepares validation specifications, evaluates IP, and generates test reports. Ensures products conform to standards and specifications.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:

  • Bachelors or Master's degree in electrical engineering or physics or computer engineering or another relevant field
  • 5+ years of experience in Memory/DDR technology
  • 5+ years of hands-on validation and debug experience at system level and memory interfaces
  • 5+ years of experience with industry-standard JEDEC memory protocols and test methodologies

Preferred Experience:

  • Understanding platform level signal integrity and power integrity technologies a definite asset
  • Experience with validation of high-speed I/O interfaces, including understanding of Tx, Rx, PLL, DLL, Clocking, and Equalization
  • Knowledge of computer architecture (CPU, DDR Memory technologies) and software/firmware architecture (bios, firmware debug experience)
  • Hands-on experience of validation & debug using tools such as Oscilloscopes, Signal generators, BERT, and Logic analyzers
  • Familiarity of Server/Xeon Memory RAS features
  • Python scripting/programming skills
  • Must be a self-starter and be able to independently drive tasks to completion
  • In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation concepts
  • Familiarity with Memory Reference Code (MRC), DDR training algorithms
  • Working knowledge of high-speed analog and digital circuits of IO

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Intel

About the company

Intel

Large Enterprise

Intel Corporation is a global leader in computing innovation, renowned for its advanced semiconductor manufacturing and technology solutions. Founded in 1968, the company is primarily known for developing microprocessors that power a vast range of computing devices, from personal computers to data centers. With a strong commitment to research and development, Intel continuously drives advancements in artificial intelligence, cloud computing, and the Internet of Things (IoT), aiming to enhance connectivity and computing capabilities around the world. Intel's mission is to create technology that enhances lives and enables progress across various industries.