ASIC Design Manager

Summary

Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Sophisticated, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next excellent Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a dedicated engineering manager to join our exciting team of problem solvers.

Description

As an ASIC Design Manager, your responsibilities span various aspects of SOC design:

- Manage a team of engineers and help them prioritize and interact with partners and customers. Help guide them with their own growth in Apple.
- Help architect solutions for power management of the SOC and other SOC level functions
- Review and write microarchitecture and/or design specifications for power management and other SOC level IPs
- Plan and work on Integration of complex IPs into the SOC and own the delivery of high quality design to the SOC
- Plan and Support all front end integration activities like Lint, CDC, Synthesis, and ECO
- Work with other specialists that are members of the IP Design, SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams
- Collaborate with software and systems teams to ensure a high quality product

Minimum Qualifications

BS and a minimum of 10 years relevant industry experience

Preferred Qualifications

Experience Managing a team and being a technical lead
Experience writing specifications and converting them to design.
Experience with multiple clock domains and asynchronous interfaces.
Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies
Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable.
Ability to communicate optimally across all internal groups
Familiarity with software and operating concepts a plus
Familiarity with scripting languages like Perl, Python, or TCL a plus

Pay & Benefits — Cupertino, California, United States

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $206,200 and $356,400, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Application Deadline

Apple accepts applications to this posting on an ongoing basis.