Design Verification Lead

Summary

At Apple we push the boundaries of innovation to create extraordinary experiences for millions of users worldwide. We are seeking a Senior Engineering Leader – in the area of Silicon Design Verification to lead one or more high-caliber verification teams in developing cutting-edge silicon IPs. In this role, you will provide technical leadership, drive best practices, and ensure the first-pass success of our silicon designs. You will play a crucial role in architecting verification methodologies, managing project execution, and fostering a culture of technical excellence within your teams.

Description

As a hands-on leader you will work closely with cross functional teams to define and implement scalable, reusable, and efficient verification strategies. You will be expected to grow and guide a team of talented verification engineers, ensuring the highest quality silicon products that meet Apple’s performance, power, and area targets. Key Responsibilities include but not limited to lead, grow and mentor a team of verification engineers, providing technical guidance, career development, and performance management. Collaborate with architecture, design, and software teams to define verification requirements, drive verification strategy, planning, environment implementation and methodology. As well as define and execute functional and power-aware verification plans, focusing on test coverage, formal verification, and assertion-based verification using SystemVerilog and UVM methodologies. You also provide technical leadership by mentoring, reviewing team members' work, and fostering a culture of innovation and collaboration. And continuously refine verification strategies to improve efficiency, speed, and completeness.

Minimum Qualifications

BS and a minimum of 20 years relevant industry experience.

Preferred Qualifications

12+ years of experience in ASIC/SoC verification, including at least 3 years in a senior leadership role managing teams of engineers.
Experience with post-silicon validation and debug.
Familiarity with performance modeling, emulation, or prototyping.
Hands-on experience with low-power design verification (UPF methodology, clock gating, power intent validation, etc.).
Understanding of mixed-signal interactions and analog modeling for verification.
Background in high-speed interfaces (e.g., PCIe, USB, DDR), power-aware verification methodologies, formal verification, and constrained-random testbenches.
Proven track record of delivering high-performance silicon with first-pass success.
Deep expertise in SystemVerilog, UVM, and modern verification methodologies.
Strong debugging and problem-solving skills for complex system-on-chip (SoC) designs.
Experience leading multi-site teams and cross-functional collaboration with architecture, design, and software groups.
Experience with coverage-driven verification methodologies and regression-driven verification strategies.
Excellent communication and leadership skills, with a proven track record of developing high-performing teams and mentoring engineers.

Application Deadline

Apple accepts applications to this posting on an ongoing basis.