Role at a glance
- Salary
- Not Disclosed
- Location
- New York, New York, United States
- Work arrangement
- On-site
- Employment
- Full-time
- Experience
- You have 8+ years hands-on experience building and running modern physical design flows (e.g., floor planning, place and route, timing closure, physical verification, power analysis) You don't need to have optimized every last detail of every flow, but you should have broad enough experience across PD that you can own a flow end-to-end and know where the risks are Beyond PD, you can read and write RTL and understand how front-end design decisions affect physical implementation—and vice versa; You think about physical design in the context of the overall chip, not just as a downstream consumer of a netlist You're interested in using software engineering techniques to improve the hardware design process, and you have experience programming in a high-level language (Python, C++, Haskell, etc.)
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Role Summary
The ASIC Physical Design Engineer helps design, test, and deploy advanced hardware as part of the Ultra Low Latency team. The role spans physical design and RTL work, with collaboration across trading, networking, and research infrastructure.
What You'll Do
- Own physical-design flows end-to-end, including floor planning, place and route, timing closure, physical verification, and power analysis.
- Read and write RTL and consider how front-end design decisions affect physical implementation, and vice versa.
- Help design, test, and deploy advanced hardware in collaboration with colleagues across the firm.
Generated from the employer's posting. Verify important details before applying.
View full postingQualifications
8+ years of hands-on experience building and running modern physical design flows, with broad enough PD experience to own a flow end-to-end. Ability to read and write RTL and understand interactions between front-end design and physical implementation. Interest in software engineering techniques for hardware design and experience programming in a high-level language such as Python, C++, or Haskell. The posting describes cross-stack experience gained either by moving from RTL design into PD or by working on a smaller team with multiple responsibilities.
Original job description
Content provided by the employer
Original job description
Content provided by the employer
About the Position
We are looking to hire an ASIC Physical Design Engineer, who is also experienced reading and writing RTL, to help us design, test and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure.
This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary.
If you've spent your career exclusively in PD, this probably isn't the right fit— but if you've worked across the stack, either because you started as an RTL designer and moved into PD, or because you were on a smaller team where you had to wear multiple hats, we'd love to talk.
We're big believers in the ability of tools to improve the productivity, reliability, and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.
About You
- You have 8+ years hands-on experience building and running modern physical design flows (e.g., floor planning, place and route, timing closure, physical verification, power analysis)
- You don't need to have optimized every last detail of every flow, but you should have broad enough experience across PD that you can own a flow end-to-end and know where the risks are
- Beyond PD, you can read and write RTL and understand how front-end design decisions affect physical implementation—and vice versa; You think about physical design in the context of the overall chip, not just as a downstream consumer of a netlist
- You're interested in using software engineering techniques to improve the hardware design process, and you have experience programming in a high-level language (Python, C++, Haskell, etc.)
If you're a recruiting agency and want to partner with us, please reach out to [email protected].
About the company
Jane Street
Large Enterprise
Jane Street is a global trading firm that specializes in quantitative and algorithmic trading across various asset classes, including equities, options, and fixed income. Founded in 2000, the company leverages advanced technology and data analytics to drive its trading strategies while maintaining a strong commitment to risk management and collaboration. Known for its dynamic and intellectually stimulating work environment, Jane Street also places a high value on continuous learning and professional development, making it an attractive workplace for individuals interested in finance, mathematics, and computer science.