Job Details:

Job Description: 

The Role and Impact:
As a SOC Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. Your expertise will directly impact product quality, enabling groundbreaking advancements in technology that drive computing innovation. Collaborating across multiple teams, you will contribute to the creation and optimization of high-performance, low-power solutions while developing methodologies that enhance efficiency and operational excellence. This is an exciting opportunity to work on complex designs that have a global impact, delivering solutions that power today's world and inspire tomorrow's possibilities.

Key Responsibilities:
- Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
- Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
- Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
- Define methodologies to produce high-quality timing models and enable efficient physical design execution.
- Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans and binning strategies.
- Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
- Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
- Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.

Qualifications:

Minimum Qualifications:

Bachelor's degree in Computer Engineering, Computer Science, or related STEM discipline and 6+ years of industry experience; OR a Master's degree in the same fields and 4+ years of experience;

5+ years of experience the following;

• SOC level static timing analysis, clock network design, and timing closure methodologies.
• Timing constraint adaptation, physical design knowledge, and optimization techniques.
• Industry-standard tools for timing analysis, extraction, and physical design.
• TCL scripting and timing budgeting processes.

Preferred Qualifications:

• A PhD in the same filed and 3+ years of experience.
• Experience collaborating across diverse teams and drive innovative solutions for SoC designs.
• Knowledge of tools, flows, and methodologies for high-performance physical design.
• Experience with SoC clocking methodologies, disciplined execution, and problem-solving in digital design.
• DFT architecture knowledge

We invite you to bring your expertise and passion for physical design and timing analysis to join us in pushing the boundaries of technology. Embrace the opportunity to make a lasting impact and deliver world-changing innovations. Apply now.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Arizona, Phoenix

Additional Locations:

US, California, Santa Clara

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.