ASIC Design Engineer — Pixel IP

Summary

Do you love creating elegant solutions to highly complex challenges? As part of our Hardware Technologies group, you’ll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices!

In this highly visible role, you will be at the center of the Pixel IP design effort to capture and display beautiful images and video. You will collaborate with all disciplines, making a critical impact getting functional products to millions of customers quickly.

Description

As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to build high performance and low power pixel processing engines. Apply your knowledge of computer architecture and digital design to create digital signal processing pipelines for capturing, improving, compressing, decompressing, and displaying digital still images and video.

In this front-end design role, your tasks will include:
• Perform digital hardware design by writing high-quality RTL, with embedded assertions and cover points.
• Writing detailed micro-architectural specifications.
• Collaborating with cross-functional teams to explore solutions that maximize performance while minimizing power and area.
• Synthesizing your design and optimize for power, timing, and area.
• Working closely with design verification and formal verification teams to debug and verify functionality and performance.

Minimum Qualifications

Bachelors Degree in EE/CE.

Preferred Qualifications

Knowledge of front-end ASIC RTL digital logic design using Verilog or System Verilog.
Strong problems-solving skills using finite state machines, pipelining, parallelism, and similar computer-architecture fundamentals.
Good collaboration skills with excellent written and verbal communication skills.
Prefer familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
Knowledge of front-end implementation tasks such as synthesis and timing/area/power analysis.
Prefer familiarity with relevant scripting languages (Python, Perl, TCL).
Familiarity with High-Level Synthesis and hardware design using SystemC/C++ languages is a plus.
Background in digital signal processing concepts is a plus.

Pay & Benefits — Sunnyvale, California, United States

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,300 and $194,700, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Application Deadline

Apple accepts applications to this posting on an ongoing basis.