Life at Intel 
 

Intel is seeking a Senior EDA Software Engineer for the Silicon Chassis team. In this technical hands-on leadership role, you will help define end-to-end automation strategy and lead development of the chassis automation tool. Chassis refers to non-compute infrastructure in any soc, which provide essential platform services and typically include interconnects, protocol bridges, clock/reset/power, security, debug/trace/analytics (DTA), RAS error logic, address maps, firmware tables etc. The chassis automation tool will collect user requirements, and translate these requirements into chassis parameters, topology and generate RTL, register definitions, integration and verification collateral for the chassis using highly parameterized and configurable sub-components.  
 
You will work directly with chassis architecture, RTL design, verification, and SOC integration teams to encode the architectural rules of the interconnect and develop a reliable, testable automation framework. You will also mentor the junior engineer joining alongside you. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.  
 
Why This Role Is Exciting : 
 

• Build a brand new automation platform by defining the tool, schema, and methodology from the ground up.  

• Directly influence next-generation SoC chassis architectures and delivery. 

• Collaborate across architecture, RTL, DV, and SoC integration teams. 

• Drive technical direction and establish best practices with broad organizational impact. 
   

Key Responsibilities 

• Architect, design, and implement a new chassis automation tool to meet requirements across multiple SoC programs, ensuring scalability, maintainability, and extensibility.  

• Analyze chassis and interconnect architecture specifications, along with high-level SoC requirements, and build tooling and infrastructure to translate these requirements into generated outputs such as RTL, RDL, verification collateral, timing, and integration artifacts.  

• Develop automation flows that convert architectural intent into concrete implementations, including topology generation, parameter derivation, register definitions, and associated collateral. 

• Integrate with frontend and backend tool flows to enable robust validation and quality checks across generated artifacts (e.g., RTL, Verilog, SDC, RDL), ensuring correctness and consistency.  

• Enable Power, Performance, and Area (PPA) optimization loops by building automation and analysis capabilities that evaluate design trade-offs and guide configuration decisions.  

• Work closely with architecture, RTL design, verification, and SoC integration teams to ensure the tool accurately captures requirements and produces outputs that meet downstream expectations.  

• Participate in and contribute to technical reviews with cross-functional stakeholders, incorporating feedback to improve tool capabilities, usability, and quality.  

• Drive end-to-end execution from initial concepts and specifications through development, deployment, and ongoing maintenance of the automation framework.  

• Lead delivery of the tool and associated outputs to multiple internal customers, balancing competing requirements, schedules, and priorities while maintaining high quality.  

• Collaborate across organizational boundaries and contribute beyond immediate role scope when needed to unblock execution and ensure overall program success.  

• Mentor and guide engineers, helping establish best practices in software design, testing, and maintainability, and elevating overall team effectiveness. 

The ideal candidate will possess the following behavioral traits: 

• Ability to interpret architecture or micro-architecture specifications and translate them into robust software implementations. 

• Excellent communication, problem-solving, and organizational skills, with a track record of delivering high-quality solutions on schedule.