Role at a glance
- Salary
- $216K – $345K/yr
- Location
- Santa Clara, California, United States
- Work arrangement
- On-site
- Employment
- Full-time
- Experience
- 15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
- Education
- PhD
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Role Summary
This Staff/Principal Solutions Architect role defines and leads the technical strategy for semiconductor test across wafer probe, package, final, and qualification test. The role partners with development, process, product engineering, and manufacturing teams to modernize test infrastructure, improve yield, and apply data-driven intelligence across the test lifecycle.
What You'll Do
- Define the comprehensive test development strategy across wafer-level and package/final/qualification test for new and existing product...
- Lead architectural trade-off decisions involving test coverage, test time, cost of test, and quality escapes across the full test flow.
- Establish architectural guidelines for test programs, Test Methods/Class structure, modularity, and reuse across ATE platforms.
- Serve as the senior liaison between build and test engineering for DFT architecture decisions and influence SoC and IP build reviews on...
- Drive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization.
- Define and maintain test roadmaps aligned to device technology roadmaps and manufacturing scale targets.
Generated from the employer's posting. Verify important details before applying.
View full postingQualifications
15+ years of semiconductor test engineering experience in a fab, IDM, or OSAT environment; extensive knowledge in at least three listed semiconductor test areas; experience with leading ATE platforms; strong DFT architecture background; proficiency in test-related scripting and automation; and experience leading multi-site, cross-functional technical initiatives.
Required
- 15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
- Extensive knowledge in at least three of: ATE platform architecture, test program development, DFT methodology, yield analysis, or test...
- Skilled in leading ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar systems.
- Strong background in DFT architectures — scan compression, MBIST, LBIST, JTAG, and related methodologies.
- Proficiency in test-related scripting and automation (Python, Perl, C++, or platform-native languages).
- Proven ability to lead multi-site technical initiatives involving multi-functional teams and influence without direct authority.
- MSEE, MSCE, MSCS, or related field (or equivalent experience).
Preferred
- Experience with mixed-signal, RF, or high-speed I/O test.
- Experience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test.
- Knowledge of test data formats (STDF, ATDF) and analytics tools (JMP, Spotfire, or custom).
- Exposure to advanced packaging test challenges (2.5D/3D, chiplets, KGD).
- Prior engagement with SEMI standards committees or ATE vendor co-development programs.
- Ph.D or equivalent experience in related field
Original job description
Content provided by the employer
Original job description
Content provided by the employer
We are seeking a Staff/Principal Solutions Architect to define and lead the technical strategy for semiconductor test. This covers wafer and package test operations from start to finish. This senior individual contributor role is central to our manufacturing and product engineering teams. You will lead the architectural vision for device testing from wafer probe to final package test. Your directive includes modernising test infrastructure, improving yield, and embedding data-driven intelligence throughout the test lifecycle. You will partner closely with development, process, product engineering, and manufacturing teams across sites to ensure our test strategy scales with increasingly complex device portfolios.
What You'll be doing:
Define the comprehensive test development strategy across wafer-level (probe/ATE) and package/final/qual test for new and existing product families.
Lead architectural trade-off decisions on test coverage, test time, cost of test, and quality escapes across the full test flow.
Establish architectural guidelines for the test program, Test Methods/Class structure, modularity, and reuse across ATE platforms (Advantest, Teradyne, etc.).
Serve as the senior liaison between build and test engineering for DFT architecture decisions — scan, BIST, JTAG, boundary scan, and embedded compression.
Influence SoC and IP build reviews to ensure testability, observability, and debug-ability
Drive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization.
Define and maintain test roadmaps aligned to device technology roadmaps and manufacturing scale targets.
Mentor senior and principal test engineers; cultivate technical standards and guidelines across the test organisation.
Engage with ATE vendors, test IP providers, and industry consortia (SEMI, JEDEC, IEEE) on emerging standards and technology directions.
What we need to see:
15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
Extensive knowledge in at least three of the following areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
Skilled in leading ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar systems.
Strong background in DFT architectures — scan compression, MBIST, LBIST, JTAG, and related methodologies.
Experience with mixed-signal, RF, or high-speed I/O test is highly valued.
Proficiency in test-related scripting and automation (Python, Perl, C++, or platform-native languages).
Proven ability to lead multi-site technical initiatives involving multi-functional teams and influence without direct authority.
MSEE, MSCE, MSCS, or related field (or equivalent experience).
Ways to stand out from the crowd
Experience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test.
Knowledge of test data formats (STDF, ATDF) and analytics tools (JMP, Spotfire, or custom).
Exposure to advanced packaging test challenges (2.5D/3D, chiplets, KGD).
Prior engagement with SEMI standards committees or ATE vendor co-development programs.
Ph.D or equivalent experience in related field
With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most thoughtful and dedicated people in the world working for us. Due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 216,000 USD - 345,000 USD.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.About the company
NVIDIA
Large Enterprise
NVIDIA is a leading technology company renowned for its graphics processing units (GPUs) and innovative computing solutions that enhance visual experiences across multiple platforms, including gaming, scientific research, and artificial intelligence. Founded in 1993, the company has expanded its offerings to include powerful AI frameworks and deep learning platforms, making significant contributions to industries such as gaming, data centers, automotive, and healthcare. NVIDIA's commitment to pushing the boundaries of visual computing continues to drive advancements in both hardware and software, positioning the company at the forefront of emerging technologies and digital transformation.
NVIDIA is a leading technology company renowned for its graphics processing units (GPUs) and innovative computing solutions that enhance visual experiences across multiple platforms, including gaming, scientific research, and artificial intelligence. Founded in 1993, the company has expanded its offerings to include powerful AI frameworks and deep learning platforms, making significant contributions to industries such as gaming, data centers, automotive, and healthcare. NVIDIA's commitment to pushing the boundaries of visual computing continues to drive advancements in both hardware and software, positioning the company at the forefront of emerging technologies and digital transformation.