Design Verification Engineer

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Design and implement testbench environments and test cases. Engage in regular meetings with design and micro architecture teams to comprehend the functional and performance objectives of the ongoing design projects. Thoroughly examine and assess design specifications to gain a comprehensive understanding of the project requirements. Identify potential areas for improvement or clarification. Establish a robust testbench methodology tailored to project requirements, ensuring efficient verification processes. Write Tests and Generate Test Coverage. Develop System Verilog checkers using UVM methodology to verify new debug features. Regularly update and enhance test cases to adapt to evolving project needs. Execute regular regression tests to validate the functionality and performance of the design under various scenarios. Analyze test failures, trace signals using tools like Verdi, and collaborate with the design team to address issues. Take ownership of individual tasks and deliverables, ensuring alignment with project goals and timelines. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.

Experience and/or education must include:

Writing System Verilog/Verilog RTL code to model digital circuits and digital designs.
Using System Verilog/Verilog for developing testbench code using logic design principles.
Using System Verilog/Verilog to debug RTL and testbench code.
Developing System Verilog/Verilog to develop test benches using randomized tests.
Developing UVM testbenches to verify functional correctness.
Using UVM testbenches and System Verilog/Verilog to ensure that specified design objectives such as performance, power are being met.
Utilizing Computer Architecture for SOC architecture and design.
Utilizing design verification concepts such as functional coverage metrics to verify SOC design.

Preferred Qualifications

N/A

Application Deadline

Apple accepts applications to this posting on an ongoing basis.