Design Verification Engineer

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Design Verification of Analog and Mixed Signal ASIC Ips and ensure bug-free first silicon for part of the System on a Chip (SoC)/IP. Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP to ensure a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage. Execute verification plans, including design bring-up, DV environment bring up, regression enabling all features, and debug of the test failures. These pre silicon verification environment creation and execution helps in making sure ASIC (Application Specific Integrated Circuits) works correctly once it is manufactured. Develop block, IP and SoC level test-benches example for camera interface, usb3 controller interface. Track and report DV progress using a variety of metrics, including bugs and coverage. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field.
Experience and/or education must include:

Using Verilog, System Verilog to create complex verification environment to simulate pre-silicon all possible use cases.
Using basics of digital design and verification to test the design and debug the failures.
Using Python to enable creation of validation scripts.
Using Computer Architecture to understand the use case of the soft IP cores and how it inter-operates with the various GPU sub-systems.
Using UVM (Universal Verification Methodology) in verification environments.
Using scripting languages like Perl to create executable scripts.
Using industry standard simulation and debugging tools such as VCS from Synopsys, Verdi debugger, or Indago debugger.
Implementing different aspects of verification flow such as constrained randomization Using functional/code coverage, assertion methodology to improve quality of pre-silicon verification and measure the completeness of pre silicon verification.

Preferred Qualifications

N/A

Application Deadline

Apple accepts applications to this posting on an ongoing basis.